In modern integrated circuit fabrication technology, units are often organized at the face of a semiconductor wafer into repeating units. It is often desirable to transmit a global signal from a peripheral portion of the integrated circuit chip to each of these integrated circuits. As the number of repeating integrated circuit units grows, the problem of routing a global signal to each of them, or to a subset of them, becomes increasingly complex.
Such a repeating circuit unit is found within a modern-day dynamic random access memory (DRAM) integrated circuit. As will be more completely described below, sense amplifiers for DRAMs are now grouped into banks that are in themselves arranged in rows and columns. Each of these banks of sense amplifiers must have routed to it a global pull-down signal, and in the case of CMOS sense amplifier designs, a global pull-up signal as well.
A conventional method of routing such pull-up and pull-down signals to each sense amplifier in the array has been to route thick conductors down the sides of the integrated circuit chip and fan out lateral or transverse signal conductors to each sense amplifier bank. As will be more completely demonstrated below, as the number of sense amplifiers grow, the required width of the signal conductors increases dramatically in order to preserve the same path of resistance. In particular, the widths of the lateral lines would have to be so wide as to add an unacceptable amount of length to each DRAM chip in the case of 4 megabit designs. A need has therefore arisen for circuits and methods for transmitting global signals to sense amplifiers in the increasingly large DRAM arrays.